A buffer circuit (e.g., I/O buffer) may interface the core circuitry of a Metal-Oxide-Semiconductor (MOS) Integrated Circuit (IC) with external Input/Output (IO) circuits. The external voltage may be supplied to an output stage of the buffer circuit through an IO pad. As the operating voltage level of constituent active elements of the core circuitry may be low (e.g., 1.8 Volts (V)) compared to the operating voltage level (e.g., 3.3 V, 5V) of the external IO circuit, the interfacing of the core circuitry with external IO circuits may lead to the constituent active elements (e.g., MOS transistors) of the core circuitry being stressed.
The stress on the constituent active elements of the core circuitry may lead to a decrease in reliability of the active elements, thereby hastening a potential failure of the core circuitry.